Overview of TDC architectures in SPAD sensors for LiDAR
Recently, there has been a keen interest in developing Light Detection and Ranging (LiDAR) systems to provide situational awareness and high-resolution environment mapping required for enabling autonomous driving. Depth sensing using Single Photon Avalanche Diode (SPAD) imagers demonstrate promising potential for this application. Timing circuits are a fundamental component in such sensors. There are different techniques adopted in literature to implement Time to Digital Converters (TDC) for LiDAR. This talk will present a comparison of these techniques and discuss the scheme to increase reliability of data along with improved resistance to background conditions, while extending the LiDAR range for the same optical power.
Dr Anastasios Vilouras
Ultra-thin CMOS technology: Bio-chemical sensing microsystem for wearable and implantable applications
Almost 60 years after the first monolithic integrated circuit, the advancements in semiconductor technology enabled the scaling of the minimum feature size down to 5nm with the roadmap moving towards 3nm by 2022. In addition, the International Semiconductor Roadmap for Semiconductors (ITRS) also considers applications which depend less on pushing the minimum feature size further down (More than Moore). Silicon is still the best suited semiconducting material for large-scale monolithic integration of complex circuits and systems offering also excellent mechanical properties. A new paradigm of silicon technology is the ultra-thin chip (UTC) technology and emerging applications. For example, very thin integrated circuits (ICs) with through-silicon vias (TSVs) will allow the stacking and interconnection of multiple dies in a compact format allowing a migration towards three-dimensional ICs (3D-ICs). Also, extremely thin, and therefore mechanically bendable silicon chips in conjunction with the emerging thin-film and organic semiconductor technologies will enhance the performance and functionality of large-area flexible electronic systems. However, UTC technology requires special attention related to the circuit design, fabrication, dicing and handling of ultra-thin chips as they have different physical properties compared to their bulky counterparts. Also, transistors and other active devices on UTCs experiencing variable bending stresses will suffer from the piezoresistive effect of the silicon substrate which results in a shift of their operating point and therefore, an additional aspect should be considered during circuit design. This talk tries to address some of these challenges related to UTC technology by focusing on the modelling of transistors on mechanically bendable Si-UTCs, the design of an integrated CMOS-based ISFET microsystem, the thinning of the CMOS ICs down to ~30m and the electrical and electrochemical characterisation of the first reported ISFET-based ultra-thin IC. Finally, this talk will present the first reported demonstration of the exploitation of the piezoresistive nature of silicon to tackle a long-standing non-ideal effect of ISFETs, i.e. the slow and temporal drift of their operating point.